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QL3025 - pASIC 3 FPGATM
25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3025 - pASIC 3 FPGA
DEVICE HIGHLIGHTS
Device Highlights Device Highlights
High Performance & High Density
s 25,000 Usable PLD Gates with 204 I/Os s 16-bit counter speeds over 300 MHz, data path speeds over
400 MHz
s 0.35um four-layer metal non-volatile CMOS process for
smallest die sizes
Easy to Use / Fast Development Cycles
s 100% routable with 100% utilization and complete
pin-out stability
s Variable-grain logic cells provide high performance and
100% utilization
s Comprehensive design tools include high quality
Verilog/VHDL synthesis
Advanced I/O Capabilites
s Interfaces with both 3.3 volt and 5.0 volt devices s PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4
FIGURE 1. 672 Logic Cells
speed grades
s Full JTAG boundary scan s Registered I/O cells with individually controlled clocks and
PRODUCT SUMMARY
Product Summary
output enables
Total of 204 I/O Pins
s 196 bidirectional input/output pins, PCI-compliant for 5.0 volt
and 3.3 volt buses for -1/-2/-3/-4 speed grades
s 4 high-drive input-only pins s 4 high-drive input/distributed network pins
The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the QL3025 is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages. Software support for the complete pASIC 3 family, including the QL3025, is available through three basic packages. The turnkey QuickWorks" package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation.
Four Low-Skew Distributed Networks
s Two array clock/control networks available to the logic cell flip-
flop clock, set and reset inputs - each driven by an input-only pin
s Six global clock/control networks available to the logic cell F1,
clock set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback
High Performance
s Input + logic cell + output total delays under 6 ns s Data path speeds over 400 MHz s Counter speeds over 300 MHz
QL3025 Rev C
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QL3025 - pASIC 3 FPGATM
QL3025 PINOUT DIAGRAM PASIC PINOUT DIAGRAMS
QL3025 Pinout Diagrams
Pin #1
Pin #109
pASIC QL3025-1PF144C
Pin #37
FIGURE 2. 144-Pin TQFP
pASIC Pinout Table
Pin #73
Pin #1
Pin #157
pASIC QL3025-1PQ208C
Pin #53
FIGURE 3. 208-Pin PQFP
Pin #105
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Preliminary
QL3025 - pASIC 3 FPGATM
144 TQFP & 208 PQFP PINOUT TABLE
144 TQFP & 208 PQFP Pinout Table
208 144 PQFP TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NC 1 2 3 NC 4 5 NC 6 7 NC NC 8 NC 9 NC 10 11 12 13 NC 14 15 16 17 18 19 20 21 22 23 NC 24 NC 25 NC 26 27 28 NC NC 29 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O 208 144 PQFP TQFP 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 30 31 NC 32 NC 33 NC 34 35 36 37 38 39 NC 40 NC NC 41 42 43 NC 44 45 NC 46 47 48 NC 49 NC 50 51 52 NC 53 54 55 56 NC 57 58 59 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O 208 144 PQFP TQFP 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 60 61 NC 62 63 NC NC 64 NC 65 66 67 NC NC 68 69 NC 70 71 72 NC 73 NC 74 75 76 77 NC 78 79 80 NC 81 82 NC 83 NC 84 85 NC 86 NC Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 208 144 PQFP TQFP 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 87 88 89 90 91 92 93 94 95 NC 96 NC 97 98 NC 99 NC 100 NC 101 102 103 104 NC 105 106 NC 107 NC 108 109 110 111 NC 112 113 NC NC 114 115 116 NC Function GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O GND I/O VCC I/O I/O I/O 208 144 PQFP TQFP 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 117 118 119 120 NC NC 121 NC 122 123 124 NC 125 126 127 128 129 NC 130 131 132 NC 133 134 NC 135 136 NC 137 NC 138 139 NC 140 NC 141 142 NC 143 144 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO I/O
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QL3025 - pASIC 3 FPGATM
256-PIN PBGA PINOUT DIAGRAM
256-Pin PBGA Pinout Diagram
pASIC QL3025-1PB256C
TOP
Pin A1 Corner
20 18 16 14 12 10 8 6 4 19 17 15 13 11 9 7 5 3 2 1 A B C D E F G H J K L M N P R T U V W Y
BOTTOM
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Preliminary
QL3025 - pASIC 3 FPGATM
PBGA 256 PINOUT TABLE
PBGA 256 Pinout Table
256 PBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 Function VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC STM NC I/O I/O I/O I/O 256 PBGA C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 Function I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VSS I/O VCC I/O VSS I/O I/O VCC I/O VSS I/O VCC I/O VSS I/O I/O I/O NC I/O I/O I/O I/O I/O 256 PBGA E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 Function I/O I/O I/O I/O I/O VCC VCC NC I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O VSS VSS I/O I/O I/O I/O I/O NC I/O NC I/O I/O GCLK / I I/O I/O I/O VCC I ACLK / I I NC I 256 PBGA L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 Function ACLK / I I GCLK / I VCC I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O VSS VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O VCC VCC I/O I/O I/O NC I/O I/O NC 256 PBGA T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 Function I/O I/O NC I/O I/O I/O I/O VSS I/O VCC I/O VSS I/O VCC I/O I/O VSS I/O VCC I/O VSS I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TMS 256 PBGA V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Function I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC
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QL3025 - pASIC 3 FPGATM
Pin Descriptions
PIN DESCRIPTIONS
Pin Descriptions
Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC VCCIO GND
Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin
Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation. Can be configured as either or both. Can be configured as either or both. Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3V supply. Connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3V supply. Connect to ground.
Ordering Information
QL 3025 - 1 PQ208 C
QuickLogic pASIC device pASIC 3 device part number Operating Range C = Commercial I = Industrial M = Military
Speed Grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = fastest
Package Code PF144 = 144-pin TQFP PQ208 = 208-pin PQFP PB256 = 256-pin PBGA
* Contact QuickLogic regarding availability
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Preliminary
QL3025 - pASIC 3 FPGATM
Absolute Maximum Ratings
VCC Voltage . . . . . . . . . . . . . . . . . . . -0.5 to 4.6V VCCIO Voltage . . . . . . . . . . . . . . . . . -0.5 to 7.0V Input Voltage . . . . . . . . . . . . -0.5 to VCCIO +0.5V Latch-up Immunity . . . . . . . . . . . . . . . . . 200 mA DC Input Current . . . . . . . . . . . . . . . . . . . 20 mA ESD Pad Protection . . . . . . . . . . . . . . . . . 2000V Storage Temperature . . . . . . . . . -65C to +150C Lead Temperature . . . . . . . . . . . . . . . . . . . 300C
Operating Range
Symbol VCC VCCIO TA TC K Parameter Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade Delay Factor -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade Military Min Max 3.0 3.6 3.0 5.5 -55 125 0.42 0.42 N/A N/A 1.64 1.37 N/A N/A Industrial Min Max 3.0 3.6 3.0 5.5 -40 85 0.43 0.43 0.43 0.43 0.43 1.90 1.54 1.28 0.90 0.82 Commercial Min Max 3.0 3.6 3.0 5.25 0 70 0.46 0.46 0.46 0.46 0.46 1.85 1.50 1.25 0.88 0.80 Unit V V C C
DC Characteristics
Symbol VIH VIL VOH VOL II IOZ CI IOS ICC ICCIO Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] D.C. Supply Current [4] D.C. Supply Current on VCCIO Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 A IOL = 16 mA [1] 0.45 V IOL = 1.5 mA 0.1VCC V VI = VCCIO or GND -10 10 A VI = VCCIO or GND -10 10 A 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 2 mA 0 100 A Conditions
Notes: [1] Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. [2] Capacitance is sample tested only. Clock pins are 12 pF maximum. [3] Only one output at a time. Duration should not exceed 30 seconds. [4] For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer engineering.
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QL3025 - pASIC 3 FPGATM
AC Characteristics at VCC = 3.3V, TA = 25C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
Input-Only/Clock Cells
Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout [5] 2 3 4 8 12 1.6 1.8 1.9 2.4 2.9 1.7 1.9 2.0 2.5 3.0 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.8 1.0 1.1 1.6 2.1 0.7 0.9 1.0 1.5 2.0 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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Preliminary
QL3025 - pASIC 3 FPGATM
Clock Cells
Symbol tACK tGCKP tGCKB Parameter Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1 1.2 0.7 0.8 Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 11 1.7 0.7 1.3
I/O Cells
Symbol tI/O tISU tIH tlOCLK tlORST tlESU tlEH Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout [5] 2 3 4 8 1.6 1.8 2.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 1.0 1.2 1.5 2.5 0.9 1.1 1.4 2.4 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0
Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ
Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 30 2.1 2.2 1.2 1.6 2.0 1.2
Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 2.5 3.1 3.6 2.6 3.2 3.7 1.7 2.2 2.8 2.0 2.6 3.1
150 4.7 4.8 3.9 4.2
Notes: [7] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. [8] The following loads are used for tPXZ:
tPHZ 1K 5 pF 1K tPLZ 5 pF
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QL3025 - pASIC 3 FPGATM
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Preliminary

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